PMOS AND NMOS IOFF CURRENT PDF

6,127,697 to Guidash describes an active pixel sensor comprising a substrate of a first conductivity type having a surface containing PMOS and NMOS implants that are indicative of a sub-micron CMOS process, a photodetector formed at a first depth from an implant of a second conductivity type that is opposite the first conductivity type on the surface, and a gate on the surface adjacent to the photodetector. The pixel combines a compact mesa-isolated PMOS access transistor with a novel, area efficient high voltage device. 6,147,362 to Keyser describes a high performance pixel for active matrix electronic displays. This invention relates to a CMOS pixel comprising an N в€’ well formed in a P в€’ epitaxial silicon layer with a dual gate PMOS transistors formed in the N в€’ well. The circuit can be expanded to form two pmos transistors sharing a common drain in the n в€’ well. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The n в€’ well forms a second gate for the dual gate pmos transistor since the potential of the n в€’ well 12 affects the conductivity of the channel of the pmos transistor. One of the p + regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The pmos transistors formed within the n в€’ well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the pmos transistors are set at a lower potential than the n в€’ well potential so that they remain reverse biased with respect to the n в€’ well. The two p + regions form the source and drain of a pmos transistor. 230000000875 corresponding Effects 0.A pixel circuit with a dual gate pmos is formed by forming two p + regions in an n в€’ well.Anticipated expiration legal-status Critical Status Expired - Lifetime legal-status Critical Current Links Assignors: Oracle America, Inc., ORACLE USA, INC., SUN MICROSYSTEMS, INC. MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: KANT, SHREE Application granted granted Critical Publication of US6316301B1 publication Critical patent/US6316301B1/en Assigned to Oracle America, Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANT Assigned to SUN MICROSYSTEMS, INC. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc Priority to US09/520,921 priority Critical patent/US6316301B1/en Assigned to SUN MICROSYSTEMS, INC. Original Assignee Sun Microsystems Inc Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime Application number US09/520,921 Inventor Shree Kant Current Assignee (The listed assignees may be inaccurate.

PMOS AND NMOS IOFF CURRENT PDF

Google Patents Method for sizing PMOS pull-up devicesДownload PDF Info Publication number US6316301B1 US6316301B1 US09/520,921 US52092100A US6316301B1 US 6316301 B1 US6316301 B1 US 6316301B1 US 52092100 A US52092100 A US 52092100A US 6316301 B1 US6316301 B1 US 6316301B1 Authority US United States Prior art keywords transistors pull nmos pmos output node Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. Google Patents US6316301B1 - Method for sizing PMOS pull-up devices US6316301B1 - Method for sizing PMOS pull-up devices

Pmos and nmos ioff current